1. Field of the Invention
Embodiments of the present invention relate to the field of communication bus interfaces. More particularly, embodiments of the present invention relate generally to the generation of an interrupt condition from a slave device in a communication network including the slave device and a master device.
2. Related Art
The I2C bus is a two wire serial bus interface and is comprised of a serial data (SDA) line and a serial clock (SCL) line. The I2C bus is controlled by a master device that coordinates communication between the master device and various slave devices over the SDA line. Because of its simplistic two wire bi-directional nature, the I2C bus maximizes hardware efficiency and circuit simplicity. The I2C bus provides more chip flexibility in function and lowers interconnecting costs by reducing board space and pin count. As such, the I2C bus is a desired choice for communication interfaces and is able to support an extremely broad range of I2C compatible chips and their corresponding devices.
Typically, the master device initiates a communication transaction with a particular slave device over the I2C bus. This can be accomplished by the master device by addressing a selected slave device with a read/write access request. A start condition may be generated over the SDA line by the master device to inform all of the devices coupled to the I2C that a communication transaction is under process. After the slave acknowledges initiation of the communication transaction, the master device can send data to the slave device or receive data from the slave device.
However, each slave device on the I2C bus may need to interrupt the master device upon an asynchronous event. For example, a slave device may inform the master device of the completion of a task, when a buffer is full or empty, etc. A typical I2C bus may handle up to 128 slave devices. Since each slave device may need to generate an interrupt signal for requesting service by the master device, the master device may require up to 128 discrete interrupt input pins.
Conventional Art FIG. 1A is a block diagram of a communication network 100A that is comprised of a master device 110 for controlling communication over the two wire serial bus 120. The communication network 100A can be comprised of a plurality of slave devices 130 coupled to the two wire serial bus 120. The plurality of slave devices 130 can be comprised of N slave devices, e.g., slave device 140, slave device 150, and slave device 160, etc.
The two wire serial bus can be comprised of a serial data (SDA) line 122 and a serial clock (SCL) line 124. Each of the plurality of slave devices 130 is coupled to the SDA line 122 in parallel. In addition, each of the plurality of slave devices 130 is coupled to the SCL line 124 in parallel.
The current practice for an I2C slave device to signal an interrupt is to use an extra interrupt (INT) pin. The INT pin is not a part of the I2C specification, but is a workable interrupt solution for implementation on a large multitude of I2C slave devices. However, the extra INT pin undesirably adds to hardware complexity and increases interconnecting costs by increasing board space and pin count.
The communication network 100A of Conventional Art FIG. 1A illustrates the implementation of an INT input pin at the master device 110 for each INT output pin in the plurality of slave devices 130. For example, INT output pin 142A of slave device 140 is coupled to the INT input pin 142B at the master device 110 via a dedicated input line 145. The INT output pin 152A of slave device 150 is coupled to the INT input pin 152B via a dedicated input line 155. Also, INT output pin 162A of slave device 160 is coupled to the INT input pin 162B via a dedicated input line 165. As such, the master device 110 would comprise N INT input pins, one for each of the INT output pins on each of the N slave devices in the plurality of slave devices 130.
The number of input and output INT pins can quickly increase within the communication network 100A. A typical communication network 100A may have three slave devices within the plurality of slave devices 130. The additional three input pins in the master device 110 represents a significant cost increase. In addition, each of the plurality of slave devices have an additional INT pin that greatly adds to their fabrication cost, or, otherwise reduces the available pin count, and ultimately the flexibility of the chip.
Assuming all slave interrupt outputs are active low, an alternative solution is to wire-AND all the interrupts together in parallel so that the master device 110 would only need one INT input pin. Conventional Art FIG. 1B illustrates a communication network 100B illustrates the implementation of an AND module 190 for signaling an interrupt. Network 100B is similar to communication network 100A in structure, except for wire-ANDing the independent and dedicated interrupt lines 165, 155, and 145.
The master devices 110 must still utilize an extra INT input pin. Also, even though the wire-AND'ing of the interrupt lines coming from the plurality of slave devices greatly reduces the input INT pin count in the master device 110, there still is a fifty percent increase to the pin count (2 pins) of the normal I2C interface, with the dedicated INT input pin at the master device 110, and each of the plurality of slave devices.
Another problem associated with the Conventional Art communication network 100B, is the tedious discovery process for the master device 110 implemented to determine which slave device may have requested an interrupt signal. After the master device 110 recognizes that an interrupt has occurred, it must read the status register of all the slave devices (e.g., 140, 150, 160, etc.) attached to the master device 110 to determine which slave device or slave devices have sent an interrupt. Multiple devices may have signaled interrupts at the same time.
The discovery process is long and tedious because each slave must be addressed and sent a status register address. Also, the master device 110 must wait for the return by the slave device polled for the contents of their interrupt status register. The process can take a minimum of three bytes per peripheral slave device. For example, at currently defined speeds (e.g., 100 kb/s, 400 kb/s, 1 Mb/s, etc) over the I2C bus, performing a possible three (1 slave) to 384 bytes (128 slaves) can take a significant response time.
One alternative solution is illustrated in Conventional Art communication network 100A, by using separate and dedicated INT pins for each I2C interrupt-enabled slave device. However, having more than one INT pin dedicated to I2C slave devices defeats the purpose of using the simplistic and efficient two wire serial bus. Also, this alternative is expensive to support in terms of hardware cost.